Zuordnung – Stand 16.09.2024

  • 1311 Lehrstuhl Eingebettete Systeme der Informationstechnik
  • 2290 Lehrstuhl Eingebettete Systeme



2024

[1]
S. S. Sahoo, S. Ullah, S. Bhattacharjee, und A. Kumar, „AxOCS: Scaling FPGA-Based Approximate Operators Using Configuration Supersampling“, IEEE transactions on circuits and systems 1, Bd. 2024, 2024, doi: 10.1109/tcsi.2024.3385333.
[2]
S. S. Sahoo, S. Ullah, und A. Kumar, „AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming“, ACM transactions on reconfigurable technology and systems, Bd. 17, Nr. 2, S. 1–28, Feb. 2024, doi: 10.1145/3648694.
[3]
S. Ullah, S. S. Sahoo, A. Kumar, und S. Ullah, „AxOSpike: Spiking Neural Networks-Driven Approximate Operator Design“, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Nov. 2024, Publiziert, doi: 10.1109/tcad.2024.3443000.
[4]
M. Eslami u. a., „MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks“, IEEE Embedded Systems Letters, Dez. 2024, Publiziert, doi: 10.1109/les.2024.3444921.

2023

[1]
Y. Liu, S. Rai, S. Ullah, und A. Kumar, „High-flexibility designs of quantized runtime reconfigurable multi-precision multipliers“, IEEE embedded systems letters / Institute of Electrical and Electronics Engineers, Bd. 15, Nr. 4, S. 194–197, Sep. 2023, doi: 10.1109/les.2023.3298736.
[2]
Y. Zhao, S. Ullah, S. S. Sahoo, und A. Kumar, „NvMISC: toward an FPGA-based emulation platform for RISC-V and nonvolatile memories“, IEEE embedded systems letters / Institute of Electrical and Electronics Engineers, Bd. 15, Nr. 4, S. 170–173, Sep. 2023, doi: 10.1109/les.2023.3299202.
[3]
S. S. Sahoo, S. Ullah, und A. Kumar, „AxOTreeS: a Tree Search Approach to Synthesizing FPGA-based Approximate Operators“, ACM transactions on embedded computing systems, Bd. 22, Nr. S 5, Art. Nr. 10, Sep. 2023, doi: 10.1145/3609096.
[4]
S. Ullah, S. S. Sahoo, und A. Kumar, „CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators“, in Proceedings of the Great Lakes Symposium on VLSI 2023, Knoxville , Mai 2023, S. 671–677. doi: 10.1145/3583781.3590222.
[5]
A. Immaneni, S. Ullah, S. Nambi, S. S. Sahoo, und A. Kumar, „PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML“, in 2022 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Jan. 2023, S. 214–223. doi: 10.1109/dsd57027.2022.00037.
[6]
S. Ullah und A. Kumar, Approximate arithmetic circuit architectures for FPGA-based systems. Cham: Springer International Publishing, 2023. doi: 10.1007/978-3-031-21294-9.
[7]
S. Ullah, S. S. Sahoo, und A. Kumar, „Designing resource-efficient hardware arithmetic for FPGA-based accelerators leveraging approximations and mixed quantizations“, in Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, S. Pasricha und M. Shafique, Hrsg. Cham: Springer International Publishing, 2023, S. 89–119. doi: 10.1007/978-3-031-19568-6_4.

2022

[1]
S. Ullah, S. S. Sahoo, N. Ahmed, D. Chaudhury, und A. Kumar, „AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems“, ACM transactions on embedded computing systems, Bd. 21, Nr. 3, Art. Nr. 29, Mai 2022, doi: 10.1145/3513262.
[2]
S. Ullah, S. Rehman, M. Shafique, und A. Kumar, „High-performance accurate and approximate multipliers for FPGA-based hardware accelerators“, IEEE transactions on computer-aided design of integrated circuits and systems / Institute of Electrical and Electronics Engineers, Bd. 41, Nr. 2, S. 211–224, Feb. 2022, doi: 10.1109/tcad.2021.3056337.
[3]
N. Neda, S. Ullah, A. Ghanbari, H. Mahdiani, M. Modarressi, und A. Kumar, „Multi-precision deep neural network acceleration on FPGAs“, in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), online, Feb. 2022, S. 454–459. doi: 10.1109/asp-dac52403.2022.9712485.
[4]
Y. Liu, S. Rai, S. Ullah, und A. Kumar, „NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture“, in FPT 2022: 2022 International Conference on Field-Programmable Technology (ICFPT), Hong Kong, Dez. 2022, Publiziert. doi: 10.1109/icfpt56656.2022.9974206.

2021

[1]
S. Ullah, T. D. A. Nguyen, und A. Kumar, „Energy-efficient low-latency signed multiplier for FPGA-based hardware accelerators“, IEEE embedded systems letters / Institute of Electrical and Electronics Engineers, Bd. 13, Nr. 2, S. 41–44, 2021, doi: 10.1109/les.2020.2995053.
[2]
S. Nambi, S. Ullah, S. S. Sahoo, A. Lohana, F. Merchant, und A. Kumar, „ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems“, IEEE access / Institute of Electrical and Electronics Engineers, Bd. 9, S. 103691–103708, Juli 2021, doi: 10.1109/access.2021.3098730.
[3]
S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, und A. Kumar, „Area-optimized accurate and approximate softcore signed multiplier architectures“, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, Bd. 70, Nr. 3, S. 384–392, 2021, doi: 10.1109/tc.2020.2988404.

2020

[1]
A. R. Baranwal, S. Ullah, S. S. Sahoo, und A. Kumar, „ReLAccS: a Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems“, IEEE transactions on computer-aided design of integrated circuits and systems / Institute of Electrical and Electronics Engineers, Bd. 40, Nr. 9, S. 1754–1767, Okt. 2020, doi: 10.1109/tcad.2020.3028350.
[2]
S. Gupta, S. Ullah, K. Ahuja, A. Tiwari, und A. Kumar, „ALigN: a Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks“, IEEE access / Institute of Electrical and Electronics Engineers, Bd. 8, S. 118899–118911, Juni 2020, doi: 10.1109/access.2020.3005286.

2018

[1]
S. Ullah u. a., „Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators“, in Proceedings of the 55th Annual Design Automation Conference, San Francisco, Juni 2018, Publiziert. doi: 10.1145/3195970.3195996.
[2]
B. S. Prabakaran u. a., „DeMAS: an efficient design methodology for building approximate adders for FPGA-based systems“, in Proceedings of the 2018 Design, Automation & Test in Europe (DATE), Dresden, Apr. 2018, S. 917–920. doi: 10.23919/date.2018.8342140.

2015

[1]
S. K. Zahid, L. Hasan, A. A. Khan, und S. Ullah, „A novel structure of the Smith-Waterman Algorithm for efficient sequence alignment“, in 2015 Third International Conference on Digital Information, Networking, and Wireless Communications (DINWC 2015), Moskau, März 2015, S. 6–9. doi: 10.1109/dinwc.2015.7054208.

2011

[1]
M. Murad, A. Rehman, A. A. Shah, S. Ullah, M. Fahad, und K. M. Yahya, „RFAIDE - An RFID based navigation and object recognition assistant for visually impaired people“, in 7th International Conference on Emerging Technologies (ICET), 2011, Islamabad, Okt. 2011, Publiziert. doi: 10.1109/icet.2011.6048486.

2010

[1]
I. Ashraf u. a., „Parameter tuning of evolutionary algorithm by Meta-EAs for WCET analysis“, in Proceedings - 2010 6th International Conference on Emerging Technologies, ICET 2010, Nov. 2010, S. 7–10. doi: 10.1109/icet.2010.5638389.
[2]
M. Asif Manzoor u. a., „Real time image registration based on feature tracking using a Digital Signal Processor“, in Proceedings - 2010 6th International Conference on Emerging Technologies, ICET 2010, Nov. 2010, S. 155–158. doi: 10.1109/icet.2010.5638499.

Nach oben

To Top