Project Description

Wide range of embedded systems found in many industrial application domains, such as automotive and avionics, are evolving into Mixed-Criticality (MC) systems, where various applications in terms of assurance levels are executed onto a common platform to meet cost, space, timing, and power consumption requirements while guaranteeing a safe operation. With the technology scaling in these modern embedded platforms, which leads to exacerbating the rate of manufacturing defects and physical fault rates, the safety and reliability issues have increased tremendously in all electronic systems, from unreliable execution of MC applications to unreliable hardware. In order to design a reliable system, fault mitigation and reliability methods need to be applied in multiple system abstraction layers. This project (Lean-MICS) investigates the feasibility of developing a hybrid ML-based cross-layer reliability design for embedded MC systems to estimate and improve the objectives of reliability, QoS, and power consumption, at design- and run-time.

Papers

  1. B. Ranjbar and A. Kumar, "AnTi-MiCS: Analytical Framework for Bounding Time in Embedded Mixed-Criticality Systems," in Proc. on International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXV), Greece, July 2025
  2. B. Ranjbar, P. Justen and A. Kumar, "GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems," in IEEE Embedded Systems Letters (ESL), vol. 17, no. 2, pp. 107-110, April 2025, doi: 10.1109/LES.2024.3466268
  3. M. Eslami et al., "MONO: Enhancing Bit-Flip Resilience with Bit Homogeneity for Neural Networks," in IEEE Embedded Systems Letters (ESL), vol. 16, no. 4, pp. 333-336, Dec. 2024, doi: 10.1109/LES.2024.3444921
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