Project description
Shrinking feature sizes has long been a major factor to improve CMOS circuit performance. This led to zero-effort performance gains in electronic circuit architecture in the…
Project description
Shrinking feature sizes has long been a major factor to improve CMOS circuit performance. This led to zero-effort performance gains in electronic circuit architecture in the…
Papers
S Märcker, M Raitza, S Rai, G Galderisi, T Mikolajick, J Trommer, A Kumar, “Formal Analysis of Camouflaged Reconfigurable Circuits”, 21st IEEE Interregional NEWCAS Conference (NEWCAS), 1-5,…
