Lectures and Laboratories



Rech­ner­ge­stütz­te Sys­tem­ana­ly­se is a com­bi­na­ti­on of lec­tu­re and la­bo­ra­to­ry. Du­ring the lec­tu­re the stu­dents get to know how mo­dern cir­cui­try si­mu­la­tor ope­ra­tes. In the la­bo­ra­to­ry the stu­dents learn how to si­mu­la­te ana­log cir­cuits with Or­CAD-PSpice. Be­gin­ning with net­lists of sim­ple pas­si­ve cir­cuits the com­ple­xi­ty rises up to OP cir­cuits and oscil­la­tors.



Lay­out-Ent­wurf in­te­grier­ter Schal­tun­gen: Du­ring this cour­se lay­out ba­sics of in­te­gra­ted cir­cuits are taught. This in­clu­des the un­der­stan­ding of the de­sign-flow of in­te­gra­ted cir­cuits as well as crea­ting lay­outs using Ca­dence de­sign soft­ware. In this la­bo­ra­to­ry the ba­sics of a stan­dard CMOS pro­cess is ex­plained first, from which layer de­fi­ni­ti­ons and de­sign-ru­les are de­ri­ved. After that sim­ple cir­cuits are de­si­gned and si­mu­la­ted. These cir­cuits are used to ex­plain the de­sign-flow for crea­ting cir­cuit lay­outs. This in­clu­des de­sign-ru­le check (DRC), An­ten­na Check, lay­out ver­sus sche­ma­tic (LVS), fil­ler ge­ne­ra­ti­on, extrac­tion of pa­ra­si­tic com­po­n­ents and si­mu­la­ti­on of the extrac­ted cir­cuit. Also cri­ti­cal is­su­es like latch-up and ESD are di­s­cus­sed.


Mas­ter-Prak­ti­kum Mi­xed-Si­gnal-De­sign in­te­grier­ter Mo­bil­funk­schal­tun­gen mit CA­DENCE: In this mas­ter la­bo­ra­to­ry the stu­dents learn how to si­mu­la­te and op­ti­mi­ze in­te­gra­ted CMOS cir­cuits. The focus of this la­bo­ra­to­ry is the de­ve­lop­ment of cir­cuits for mo­bi­le com­mu­ni­ca­ti­ons like low noise am­pli­fiers, mi­xers, ana­log to di­gi­tal con­ver­ters, phase lo­cked loops, et ce­te­ra. The stu­dents team up in groups of two, si­mu­la­te a de­di­ca­ted com­po­nent and op­ti­mi­ze it to meet the spe­ci­fi­ca­ti­on. The la­bo­ra­to­ry takes place for 3 hours once a week. At the end of the cour­se the stu­dents pre­sent their re­sults to get their cer­ti­fi­ca­ti­on. The crea­ted cir­cuits and lay­outs are based on the gpdk090 pro­cess de­sign-kit from Ca­dence.

Ca­dence is a re­gis­te­red trade­mark of Ca­dence De­sign Sys­tems, Inc., 2655 Seely Ave­nue, San Jose, CA 95134.

Research Activities



The re­se­arch group's main tar­get is the de­ve­lop­ment and op­ti­miza­t­i­on of new con­cepts for in­te­gra­ted cir­cuits. Star­ting point for se­ar­ching new ana­lo­gue and di­gi­tal sys­tem so­lu­ti­ons are stan­dard CMOS pro­ces­ses with sta­te-of-the-art chan­nel lengths. To de­ve­lop new in­no­va­ti­ve con­cepts for ana­lo­gue and di­gi­tal func­tio­nal groups, the exact know­ledge about the elec­tri­cal be­ha­vi­or of in­te­gra­ted cir­cuits and the ac­cu­ra­cy of their be­ha­vio­ral mo­dels is ne­cessa­ry. In par­ti­cu­lar pa­ra­si­tic ef­fects play a major role in this con­text. By using dif­fe­rent com­pu­ter aided me­thods the re­se­arch group from Bo­chum is wor­king on over­co­ming the li­mits of known stan­dards to show new ways and pos­si­bi­li­ties for the de­ve­lop­ment of in­te­gra­ted cir­cuits. The­re­fo­re it is es­sen­ti­al to mi­ni­mi­ze the ef­fects of pa­ra­si­tics or to use them con­struc­tive­ly in com­bi­na­ti­on with other phy­si­cal ef­fects. The re­se­ar­chers in­clu­de these de­sign de­pen­den­cies, which af­fect the sys­te­ma­tic and sta­tis­tic matching of in­te­gra­ted cir­cuits to find new con­cepts and sys­tem so­lu­ti­ons. Cur­rent re­se­arch to­pics are op­ti­cal sys­tems in stan­dard CMOS, mis­match in in­te­gra­ted cir­cuits and me­thods to prevent si­de-chan­nel at­tacks.


The main focus of the re­se­arch lays on di­gi­tal com­mu­ni­ca­ti­ons as well as high speed and high per­for­mance ana­log cir­cuits. In the early days of the chair the first di­gi­tal high speed cir­cuits up to 40 GBit/s in Si­Ge-Tech­no­lo­gy were de­ve­lo­ped. No­wa­days the main in­te­rest is fo­cu­sed on mo­bi­le com­mu­ni­ca­ti­on with a wide know­ledge in ana­log cir­cuits like LNAs, mi­xers, base­band cir­cuits and ADCs. Fur­ther re­se­arch is done in power op­ti­miza­t­i­on in the di­gi­tal base­band for UMTS and pro­to­col stack op­ti­miza­t­i­on in mo­bi­le multi core pro­ces­sors for fu­ture mo­bi­le com­mu­ni­ca­ti­on stan­dards. Ano­ther in­te­res­ting re­se­arch area is the fill level me­a­su­re­ment in oil tanks using wide range radar. The chair de­ve­lo­ped a low power 80 GHz oscil­la­tor with a tu­ning range of 24.5 GHz in a Si­Ge-Tech­no­lo­gy. Using this oscil­la­tor in an FM­CW-Ra­dar leads to a dis­tan­ce me­a­su­re­ment with a re­so­lu­ti­on of a few mil­li­me­ters. Ano­ther re­se­arch topic is ad­dres­sed in the pro­ject RoCC (Ra­dar-on-chip-for-cars). The main goal of this pro­ject is to cope with the in­crea­sed traf­fic to im­pro­ve the sa­fe­ty of all. The chair is de­ve­lo­ping dif­fe­rent trans­cei­ver ar­chi­tec­tu­res for au­to­mo­ti­ve radar sys­tems which can be used in pre-crash sen­sors and brake as­sist sys­tems.

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