Forschung
Nachstehend finden Sie eine Liste der finanzierten Forschungsprojekte an unserem Lehrstuhl.
Aktive Forschungsprojekte und Kollaborationen
LeanMICS: Learning-Based Cross-Layer Reliability Management in Embedded Mixed-Criticality Systems
SecuReFET II: Secure Circuits through inherent Reconfigurable FET II
DART: Design Automation for Reconfigurable Transistors
Project description
Shrinking feature sizes has long been a major factor to improve CMOS circuit performance. This led to zero-effort performance gains in electronic circuit architecture in the past. By approaching the power wall for current CMOS scaling factors we see an increased need for thermal management and the need to employ dark silicon schemes to provide both the necessary performance and utility at the same time. In this project, we investigate the possibilities for reconfigurable transistors to reshape electronic circuit design to provide a higher functional density while maintaining sufficiently low power consumption. To achieve this, we exploit unique properties like multiple gates per transistor next to their reconfigurability. We focus on a model-based approach to design a new standard cell library by using probabilistic model checking. For this we extend a model checker to design and verify new cells. In close collaboration with nanomaterials research we refine our models to fit the projections and laboratory implementations of emerging technology devices. The new standard cell library will not only map current CMOS cell designs to new technology but will also cover new cells with a higher complexity and thus functionality. We expect that this will put greater load on to the logic synthesis that is responsible for standard cell selection. We also take the logic synthesis flow into account. While an unmodified EDA flow will produce preliminary results, we expect that modifications to technology mapping that take circuit reconfigurability and different cell properties into account will be needed to take full advantage of the new possibilities. Close communication between the model-approach and the EDA flow may also make a logic synthesis approach feasible that circumvents the limitations of current standard-cell-based EDA approaches. We design a comprehensive testing and benchmarking framework. This allows us to not only compare our new design flow against a CMOS EDA flow, but also allows us to track our own progress in standard cell design and modifications to the EDA flow. The applicant has extensive knowledge and research experience in reconfigurable architecture designs. For example, he has recently proposed novel approaches to compute the routing for FPGA-based systems and successfully tackled the problem of floorplanning runtime-reconfigurable design to increase design utility and density. He has also done significant research in improving EDA for emerging nanotechnologies. Various tool flows have been released as open-source for the benefit of the research community. Most of the work has been published at top conference venues like DAC, DATE and ICCAD, and reputed IEEE transactions. We therefore see significant potential for further high-profile publications.
Employee responsible
Papers
S Märcker, M Raitza, S Rai, G Galderisi, T Mikolajick, J Trommer, A Kumar, “Formal Analysis of Camouflaged Reconfigurable Circuits”, 21st IEEE Interregional NEWCAS Conference (NEWCAS), 1-5, 2023
X-ReAp: Cross(X)-Layer Runtime Reconfigurable Approximate Architecture
X-DNet: Energy-Efficient Distributed and In-Network Computing via Cross-Layer ApproXimation of Applications and Accelerators Software Campus (BMBF)
Developing energy-efficient and real-time solutions are from the main challenges in the era of 5G/6G, especially considering the ever-increasing complexity of computational algorithms in stream processing and AI-based applications. To address these concerns, computing is envisioned to become distributed and/or performed on-the-fly, while data is transmitted through the network elements (dubbed as In-Network Computing). In this context, the goal of X-DNet project is to improve performance- and energy-efficiency, through a HW/SW co-design approach. To achieve this end, we first reduce the complexity of applications using various ‘approximate computing’ techniques. Afterwards, we design different accelerator configurations, to be deployed in various network elements within the edge-to-cloud continuum.
TRR404 "Next Generation Electronics With Active Devices in Three Dimensions [Active-3D]"
The TRR404 "Next Generation Electronics With Active Devices in Three Dimensions [Active-3D]" is a Collaborative Research Center/Transregio between multiple universities/research centers. The role of our group is to assess complex circuit and system options for Active-3D environment, and to automate design environment for new 3D architectures. The central function of our group in this project is to develop and maintain a simplified electronic design automation environment that will allow the design of more complex systems in later phases. This is a crucial task since Active-3D eliminates boundaries between supply voltage and signals, memory, logic, and so forth, and therefore, new automated design strategies will be required and will need significant research and continuous interaction with all other project members.
DI-ReDesign: Reconfigurable open source libraries and design tools for novel transistor technologies
The project aims to create an open design library for the development of integrated circuits with reconfigurable field-effect transistors (RFETs). Furthermore, an open-source toolchain will be developed and made available to facilitate industrial access to manufacturing using the new RFET technology for chip development. A special focus is also placed on exploring novel approaches for enhanced hardware security. Finally, resilience against structural side-channel attacks using optical and electron beam techniques will be demonstrated. This project is a multi-partner project between GLOBALFOUNDRIES LLC & Co. KG, Dresden, Ruhr University Bochum, University of Bremen, Fraunhofer Institute for Microstructure of Materials and Systems IMWS, and Technical University of Berlin.
