This project focuses on leveraging Reconfigurable Field-Effect Transistors (RFETs) and Ferroelectric FETs (FeRFETs) to develop next-generation in-memory computing (IMC) architectures. The goal is to overcome the memory–compute bottleneck by enabling computation directly within memory arrays, significantly improving energy efficiency, performance, and security.

RFETs offer polarity programmability, allowing dynamic reconfiguration of logic and memory functionalities, while FeRFETs provide non-volatile ferroelectric switching, enabling compact, ultra-low-power memory elements. By combining the strengths of these emerging devices, the project aims to explore:

• Novel IMC primitives implemented using RFET/FeRFET device characteristics
• Design of neuromorphic or logic-in-memory architectures
• Techniques to enhance hardware-level security using inherent device properties

The research involves device-to-architecture co-design, simulation of emerging technology nodes, and development of prototype circuits to study functional accuracy, robustness, and scalability.

Prerequisites

• Solid foundation in Digital Design and VLSI
• Familiarity with Cadence Spectre, SPICE simulators
• Experience with Verilog/VHDL for circuit modeling
• Scripting/programming experience (Python MATLAB)

Skills You Will Gain

• Understanding of RFET and FeRFET device operation
• In-memory computing design (IMC/processing-in-memory/logic-in-memory)
• Device–circuit–architecture co-design
• SPICE-level simulation and performance/power analysis
• Experience preparing research manuscripts for journals and conferences

Contact: Syed Farah Naz

Modern heterogeneous Systems-on-Chips (SoCs) achieve high efficiency by pairing general-purpose processors with specialized hardware accelerators. Determining the optimal configuration of these components requires systematic Design Space Exploration (DSE). This project focuses on the resource-aware design of an open-source edge AI SoC. You will use an existing SoC reference design (based on components from the PULP platform) to design custom ML accelerators, integrate them into the SoC, and develop benchmark workloads for evaluation. You will analyze how different architectural configurations impact Power, Performance, and Area (PPA) of the entire SoC.

Tasks and Responsibilities

• Accelerator and SoC Architecture: Develop and integrate custom hardware accelerators into an existing RISC-V based SoC platform.
• Benchmarks and Evaluation: Develop benchmarks that run representative workloads to evaluate system performance.
• Design Space Exploration: Formulate research questions and analyze multi-dimensional tradeoffs (e.g. optimizing dataflow for offloading, or balancing the power and area cost of an accelerator vs running workloads solely on the main CPU).  
• FPGA Prototyping: Deploy the resulting SoC architecture onto an FPGA to extract PPA metrics (clock frequency, area, power).
• Optional ASIC Assessment: Evaluate PPA for ASIC implementations using open-source EDA tools (e.g. OpenROAD/LibreLane).

Learning Outcomes

• Design Space Exploration: Hands-on experience with DSE and architectural evaluation of modern heterogeneous MPSoCs.
• Frontend Flow: Practical experience with RTL-level design, system integration, and verification.
• FPGA Prototyping: Knowledge of mapping SoC designs to FPGAs and evaluating PPA under realistic workloads.

Prerequisites

• Basic RTL knowledge (SystemVerilog/VHDL) or willingness to learn, paired with a solid understanding of computer architecture concepts.
• Programming skills for scripting and workflow automation (Python, C++, Bash).
• Interest in open-source chip design, SoCs, and HW/SW-Codesign. 

Note: The specific scope, complexity, and research focus of this project will be adapted to suit the requirements of bachelor / master theses, or student researcher positions.

Contact: Mikail Yayla

To design highly efficient next-generation edge AI hardware, such as Multiprocessor System-on-Chips (MPSoCs) with powerful CPUs, NPUs, GPUs, and other types of accelerators, researchers need a comprehensive suite of application benchmarks. This project contributes to the core infrastructure of our chair by expanding our internal Model Zoo. In this thesis, you will implement, train, optimize, and deploy neural networks (NNs) selected from a wide variety of state-of-the-art architectures. This benchmark collection will allow our researchers to evaluate novel HW/SW-Codesign methods against the physical realities of resource-constrained embedded systems.

Tasks and responsibilities:

• Benchmark Selection: Integrate state-of-the-art NN architectures across a wide spectrum of domains, including but not limited to, popular architectures such as MobileNet, ResNet, ViT, YOLO, compact Large Language Models (LLMs), and combinations such as vision-language-action (VLA) models.
• Resource-Aware Design: Tailor the NNs to strict hardware constraints, targeting metrics such as the number of NN parameters, operations, and memory bandwidth, while still achieving high accuracy.
• Model Quantization and Pruning: Implement and evaluate state-of-the-art quantization techniques (down to aggressive low bit-widths, e.g. binary, ternary, or other types of low-bit quantization), pruning, or other types of compression.
• Performance Profiling: Profile efficiency metrics of the NNs, such as execution time, throughput, and memory demand, using simulators or real embedded platforms.

Example application areas to create benchmarks for:

• Computer Vision (CV): Image classification, object detection, and semantic segmentation (e.g. control automation, real-time object tracking, autonomous driving).
• Natural Language Processing (NLP): Understanding and generating human text (e.g. on-device machine translation, context summarization, localized conversational agents).
• Speech and Audio: Acoustic signal modeling, voice recognition, speech-to-text translation, and speaker identification systems.
• Time-Series Analysis: Analyzing temporal sequence data for predictions and anomaly detection (e.g. predictive maintenance telemetry, industrial IoT monitoring).
• Multimodal and Robotics (VLM / VLA): Integrating vision-language models and vision-language-action models to translate multi-sensory inputs into physical control primitives for robotic manipulation.
• Reinforcement Learning and GenAI: Exploring edge integration for RL agents and emerging local GenAI operation.

Prerequisites and skills needed:

• Programming experience in Python or a comparable object-oriented language.
• Basic knowledge of scripting tools and automation (e.g. bash scripting for training pipelines).
• Basic understanding of ML and NNs.

What you will learn:

• Training modern NN architectures from scratch using industry-standard frameworks and tools.
• Optimization and compression of NNs for future edge AI platforms.
• Managing GPU cluster resources.

Note: The specific scope, complexity, and research focus of this project will be adapted to suit the requirements of bachelor / master theses, or student researcher positions. 

Contact: Mikail Yayla