Prof. Dr. Akash Kumar

(© RUB/Marquard)

Professor

Address
Ruhr-Universität Bochum

Fakultät für Elektrotechnik und Informationstechnik
Embedded Systems
Postbox ID 29

Universitätsstraße 150
44801 Bochum

Room:
ID 2/609

Phone Extension:
(+49)(0)234 / 32 - 15677

(© RUB/Marquard)

since 2024 Professor, Chair of Embedded Systems, Ruhr University Bochum, Germany
2015 – 2024 Professor, Chair of Processor Design, TU Dresden, Germany
2011 – 2015 Assistant Professor, National University of Singapore (NUS), Singapore
2009 – 2011 Visiting Fellow, National University of Singapore (NUS), Singapore
2005 – 2009 Eindhoven University of Technology (TUe) & National University of Singapore,
PhD thesis title: Analysis, Management and Design of Multimedia Multiprocessor Systems
2003 – 2004 National University of Singapore & Eindhoven University of Technology (TUe),
Master of Technological Design (Embedded Systems
1999 – 2002 National University of Singapore (NUS),
accelerated B. Eng. (Computer Engineering) Program, First Class Honours

Design automation of embedded systems, reliability optimization, fault-tolerant and predictable architecture design, approximate computing, electronic design automation for FPGAs and emerging technology, partially reconfigurable architectures.

Ongoing research projects:

  • Lean-MICS: Learning-Based Cross-Layer Reliability Management in Embedded Mixed-Criticality Systems, DFG
    Principal Investigator, 04/2024-03/2027
  • SecuREFET-II: Secure circuits through inherent reconfigurable FET-II, DFG Special Priority Program.
    Principal Investigator, 04/2024-03/2027
  • Hardware Architecture and Platform for Cognitive Science, Sino German Center
    Principal Investigator, 11/2022-10/2025.
  • DART: Design Automation for Reconfigurable Transistors, DFG
    Principal Investigator, 9/2022-8/2025
  • X-DNet: Energy-Efficient Distributed and In-Network Computing via Cross-Layer ApproXimation of Applications and Accelerators Software Campus (BMBF)
    Principal Investigator, 04/2023-12/2025
  • X-ReAp: Cross(X)-Layer Runtime Reconfigurable Approximate Architecture, DFG
    Principal Investigator, 1/2022-12/2024.

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