Dr.-Ing. Salim Ullah
Postdoc
Address:
Ruhr University Bochum
Faculty of Electrical Engineering and Information Technology
Embedded Systems
Postbox ID 29
Universitätsstraße 150
D-44801 Bochum
Room:
ID 2/605
Phone:
(+49)(0)234 / 32 - 15685
Email:
salim.ullah(at)rub.de
2024
[1]
S. S. Sahoo, S. Ullah, S. Bhattacharjee, and A. Kumar, ‘AxOCS: Scaling FPGA-Based Approximate Operators Using Configuration Supersampling’, IEEE transactions on circuits and systems 1, vol. 2024, 2024, doi: 10.1109/tcsi.2024.3385333.
[2]
S. S. Sahoo, S. Ullah, and A. Kumar, ‘AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming’, ACM transactions on reconfigurable technology and systems, vol. 17, no. 2, pp. 1–28, Feb. 2024, doi: 10.1145/3648694.
[3]
S. Ullah, S. S. Sahoo, and A. Kumar, ‘AxOSpike: Spiking Neural Networks-Driven Approximate Operator Design’, IEEE transactions on computer-aided design of integrated circuits and systems / Institute of Electrical and Electronics Engineers, vol. 43, no. 11, pp. 3324–3335, Nov. 2024, doi: 10.1109/tcad.2024.3443000.
[4]
M. Eslami et al., ‘MONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks’, IEEE embedded systems letters / Institute of Electrical and Electronics Engineers, vol. 16, no. 4, pp. 333–336, Dec. 2024, doi: 10.1109/les.2024.3444921.
2023
[1]
Y. Liu, S. Rai, S. Ullah, and A. Kumar, ‘High-flexibility designs of quantized runtime reconfigurable multi-precision multipliers’, IEEE embedded systems letters / Institute of Electrical and Electronics Engineers, vol. 15, no. 4, pp. 194–197, Sep. 2023, doi: 10.1109/les.2023.3298736.
[2]
Y. Zhao, S. Ullah, S. S. Sahoo, and A. Kumar, ‘NvMISC: toward an FPGA-based emulation platform for RISC-V and nonvolatile memories’, IEEE embedded systems letters / Institute of Electrical and Electronics Engineers, vol. 15, no. 4, pp. 170–173, Sep. 2023, doi: 10.1109/les.2023.3299202.
[3]
S. S. Sahoo, S. Ullah, and A. Kumar, ‘AxOTreeS: a Tree Search Approach to Synthesizing FPGA-based Approximate Operators’, ACM transactions on embedded computing systems, vol. 22, no. S 5, Art. no. 10, Sep. 2023, doi: 10.1145/3609096.
[4]
S. Ullah, S. S. Sahoo, and A. Kumar, ‘CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators’, in Proceedings of the Great Lakes Symposium on VLSI 2023, Knoxville , May 2023, pp. 671–677. doi: 10.1145/3583781.3590222.
[5]
A. Immaneni, S. Ullah, S. Nambi, S. S. Sahoo, and A. Kumar, ‘PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML’, in 2022 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Jan. 2023, pp. 214–223. doi: 10.1109/dsd57027.2022.00037.
[6]
S. Ullah and A. Kumar, Approximate arithmetic circuit architectures for FPGA-based systems. Cham: Springer International Publishing, 2023. doi: 10.1007/978-3-031-21294-9.
[7]
S. Ullah, S. S. Sahoo, and A. Kumar, ‘Designing resource-efficient hardware arithmetic for FPGA-based accelerators leveraging approximations and mixed quantizations’, in Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, S. Pasricha and M. Shafique, Eds. Cham: Springer International Publishing, 2023, pp. 89–119. doi: 10.1007/978-3-031-19568-6_4.
2022
[1]
S. Ullah, S. S. Sahoo, N. Ahmed, D. Chaudhury, and A. Kumar, ‘AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems’, ACM transactions on embedded computing systems, vol. 21, no. 3, Art. no. 29, May 2022, doi: 10.1145/3513262.
[2]
S. Ullah, S. Rehman, M. Shafique, and A. Kumar, ‘High-performance accurate and approximate multipliers for FPGA-based hardware accelerators’, IEEE transactions on computer-aided design of integrated circuits and systems / Institute of Electrical and Electronics Engineers, vol. 41, no. 2, pp. 211–224, Feb. 2022, doi: 10.1109/tcad.2021.3056337.
[3]
N. Neda, S. Ullah, A. Ghanbari, H. Mahdiani, M. Modarressi, and A. Kumar, ‘Multi-precision deep neural network acceleration on FPGAs’, in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), online, Feb. 2022, pp. 454–459. doi: 10.1109/asp-dac52403.2022.9712485.
[4]
Y. Liu, S. Rai, S. Ullah, and A. Kumar, ‘NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture’, in FPT 2022: 2022 International Conference on Field-Programmable Technology (ICFPT), Hong Kong, Dec. 2022, Published. doi: 10.1109/icfpt56656.2022.9974206.
2021
[1]
S. Ullah, T. D. A. Nguyen, and A. Kumar, ‘Energy-efficient low-latency signed multiplier for FPGA-based hardware accelerators’, IEEE embedded systems letters / Institute of Electrical and Electronics Engineers, vol. 13, no. 2, pp. 41–44, 2021, doi: 10.1109/les.2020.2995053.
[2]
S. Nambi, S. Ullah, S. S. Sahoo, A. Lohana, F. Merchant, and A. Kumar, ‘ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems’, IEEE access / Institute of Electrical and Electronics Engineers, vol. 9, pp. 103691–103708, Jul. 2021, doi: 10.1109/access.2021.3098730.
[3]
S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman, and A. Kumar, ‘Area-optimized accurate and approximate softcore signed multiplier architectures’, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, vol. 70, no. 3, pp. 384–392, 2021, doi: 10.1109/tc.2020.2988404.
2020
[1]
A. R. Baranwal, S. Ullah, S. S. Sahoo, and A. Kumar, ‘ReLAccS: a Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems’, IEEE transactions on computer-aided design of integrated circuits and systems / Institute of Electrical and Electronics Engineers, vol. 40, no. 9, pp. 1754–1767, Oct. 2020, doi: 10.1109/tcad.2020.3028350.
[2]
S. Gupta, S. Ullah, K. Ahuja, A. Tiwari, and A. Kumar, ‘ALigN: a Highly Accurate Adaptive Layerwise Log_2_Lead Quantization of Pre-Trained Neural Networks’, IEEE access / Institute of Electrical and Electronics Engineers, vol. 8, pp. 118899–118911, Jun. 2020, doi: 10.1109/access.2020.3005286.
2018
[1]
S. Ullah et al., ‘Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators’, in Proceedings of the 55th Annual Design Automation Conference, San Francisco, Jun. 2018, Published. doi: 10.1145/3195970.3195996.
[2]
B. S. Prabakaran et al., ‘DeMAS: an efficient design methodology for building approximate adders for FPGA-based systems’, in Proceedings of the 2018 Design, Automation & Test in Europe (DATE), Dresden, Apr. 2018, pp. 917–920. doi: 10.23919/date.2018.8342140.
2015
[1]
S. K. Zahid, L. Hasan, A. A. Khan, and S. Ullah, ‘A novel structure of the Smith-Waterman Algorithm for efficient sequence alignment’, in 2015 Third International Conference on Digital Information, Networking, and Wireless Communications (DINWC 2015), Moskau, Mar. 2015, pp. 6–9. doi: 10.1109/dinwc.2015.7054208.
2011
[1]
M. Murad, A. Rehman, A. A. Shah, S. Ullah, M. Fahad, and K. M. Yahya, ‘RFAIDE - An RFID based navigation and object recognition assistant for visually impaired people’, in 7th International Conference on Emerging Technologies (ICET), 2011, Islamabad, Oct. 2011, Published. doi: 10.1109/icet.2011.6048486.
2010
[1]
I. Ashraf et al., ‘Parameter tuning of evolutionary algorithm by Meta-EAs for WCET analysis’, in Proceedings - 2010 6th International Conference on Emerging Technologies, ICET 2010, Nov. 2010, pp. 7–10. doi: 10.1109/icet.2010.5638389.
[2]
M. Asif Manzoor et al., ‘Real time image registration based on feature tracking using a Digital Signal Processor’, in Proceedings - 2010 6th International Conference on Emerging Technologies, ICET 2010, Nov. 2010, pp. 155–158. doi: 10.1109/icet.2010.5638499.
