The Duration is June to December 2026. The application deadline is Feb. 28th, 2026. Interested students should send their applications to Behnaz Ranjbar.

High-quality photography is critical in medical applications, particularly in environments with limited space, poor lighting, and reflective surfaces. This project focuses on the development of an embedded camera system designed to standardize and simplify the process of capturing consistent, high-quality images for reliable documentation and analysis, even under challenging conditions. The goal is to deliver a functional embedded prototype that is technically robust, efficient, and user-friendly, suitable for evaluating real-world applications.

The role will involve concept development, hardware-software co-design, and embedded system implementation, including the integration of sensors, image processing algorithms, and control systems. The goal is to deliver a functional embedded prototype that is technically robust, energy-efficient, and user-friendly, suitable for real-world applications in medical and other demanding environments. Key tasks include:

• Designing and optimizing embedded hardware for camera control and image acquisition.
• Implementing real-time image enhancement and processing algorithms on resource-constrained platforms.
• Integrating sensors, lighting modules, and control systems for adaptive image capture.
• Ensuring energy efficiency, low-latency operation, and robustness in medical and other demanding environments.

Contact information for more details: Prof. Akash Kumar

To improve the energy consumption and/or the response time of ML applications, various computing approaches have emerged in the era of 5G/6G. These approaches include Federated Learning, Distributed Inference, In-Network Computing, etc. However, to enable the execution of many cutting-edge and compute-intensive models (e.g., LLMs and DNNs) for the resource-constrained devices in the edge-to-cloud continuum, the structure of such models should be optimized without compromising the final quality of results. In this context, Approximate Computing techniques have been shown to provide highly beneficial solutions by exploiting the inherent error resiliency of ML models. Considering such potentials, the main idea in this project is to find and apply a combination of suitable approximation techniques that can reduce the area/power/energy of ML models and boost their performance while satisfying the accuracy requirement of the users.

Required skills

• FPGA development and programming: Verilog or VHDL, C++, and Python
• High-Level-Synthesis: Vivado and Vitis HLS
• ML: Tensorflow and/or PyTorch, able to change the structure of ML modes (NNs, LLMs, etc.) by applying techniques such as layer-wise quantization and pruning.

Contact information for more details: Zahra Ebrahimi

The run-time reconfigurability and high parallelism offered by FPGAs make them an attractive choice for implementing hardware accelerators for ML algorithms. In the quest for designing efficient FPGA-based hardware accelerators for ML algorithms, the inherent error-resilience of ML algorithms can be exploited to implement approximate hardware accelerators to trade the output accuracy with better overall performance. As multiplication and addition are the two main arithmetic operations in ML algorithms, most state-of-the-art approximate accelerators have considered approximate architectures for these operations. However, these works have mainly considered the exploration and selection of approximate operators from an existing set of operators. To this end, this project focuses on designing a reinforcement learning (RL)-based framework for synthesizing and implementing novel approximate operators. RL is a type of machine learning where an agent learns to perform actions in an environment to maximize a reward signal. RL-based techniques would help achieve approximate operators with better accuracy-performance trade-offs in this project.

• Pre-requisites:
  • Digital Design, FPGA-based accelerator design
  • Python, TCL
  • Some knowledge of ML algorithms
• Skills that will be acquired during project work:
  • ML for EDA
  • Multi-objective optimization of hardware accelerators.
  • Technical writing for research publications.
• Related Publications:
  • S. Ullah, S. S. Sahoo, and A. Kumar. "CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators." Proceedings of the Great Lakes Symposium on VLSI 2023. 2023.
  • S. Ullah, S. S. Sahoo, N. Ahmed, D. Chaudhury, and A. Kumar "AppAxO: Designing App lication-specific Approximate Operators for FPGA-based Embedded Systems." ACM Transactions on Embedded Computing Systems (TECS) 21.3 (2022): 1-31.
  • S. Ullah, S. S. Sahoo, A. Kumar, "CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems", In Proceeding: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1-6, Jul 2021.
• Contact: Salim Ullah

In general, there are three categories of ML techniques -- supervised-learning, unsupervised-learning, and reinforcement-learning -- where depending on the problem, parameters, and inputs, only some of these techniques are suitable and used for system properties optimization. These ML techniques are memory-intensive and computationally expensive, which makes some of them incompatible with real-time system design due to the overheads, which may cause an effect on applications' timeliness. Therefore, this project aims to analyze and investigate various ML techniques in terms of overheads, accuracy, and capability and determine the efficient ones suitable for embedded real-time systems.

• Pre-Requisites
  • Proficiency in C++, Python, Matlab
  • Knowledge about Machine Learning techniques
  • Good knowledge of computer architecture and algorithm design
• Related Publications:
  • S. Pagani, P. D. S. Manoj, A. Jantsch and J. Henkel, "Machine Learning for Power, Energy, and Thermal Management on Multicore Processors: A Survey," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 1, pp. 101-116, 2020.
• Contact
  • Behnaz Ranjbar