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We are proud to announce that Zahra, our research associate, has been awarded the AI Founder Fellowship by the Mission KI program - an initiative of acatech, the German Academy of Engineering - funded by the Federal Ministry for Digital and Transport (BMDV). This prestigious fellowship, presented by Dr. Volker Wissing, Federal Minister of the BMDV, will enable us to advance our Software Campus project, X-DNet, to the next level. Beyond the grant, Zahra will participate in various entrepreneurship training programs over the next 9 months to acquire the necessary skills for promoting our new project, GREEN-DNN, which aims to address sustainability challenges in AI within the 5G/6G era.

The DFG Granted project TRR404 "Next Generation Electronics With Active Devices in Three Dimensions [Active-3D]" is a collaborative Research Center/Transregio. It aims at exploring a completely new approach for microelectronics technology and therefore teams up materialists, electrical engineers, and computer scientists of TU Dresden, RWTH Aachen and Gesellschaft für Angewandte Mikro- und Optoelektronik mbH (AMO) in Aachen, Forschungszentrum Jülich (FZJ), Max Planck Institute of Microstructure Physics Halle (MPI-MSP), Nanoelectronic Materials Laboratory gGmbH (NaMLab) in Dresden, and Ruhr-Universität Bochum (RUB). 

Active-3D proposes to design novel 3D architectures with emerging technologies for logic, memory, and routing. These novel components in all three domains will bring in new hitherto unseen functionalities. Many of these components are expected to bring in recon gurable features where a component can function as both a logic and memory device, or another which can compute and route signals. Such components blur the distinction between the traditional logic, memory, and routing components. Traditional EDA algorithms are unable to deal with such unseen exibility in the available devices. In particular, traditional EDA algorithms separate the process of mapping the desired functionality to the available components (split into logic and memory) and the process of routing between these mapped components. Hence, novel algorithms that are able to design e cient circuits by exploiting the bene ts brought in by the novel devices being developed in this project are necessary.

This TRR includes multiple projects and the Chair of Embedded System, led by Prof. Akash Kumar leads project B05, which focuses on joint Logic, Memory, and Routing Synthesis. The initial funding phase runs from April 2025 until December 2028.